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po wer ma nage m ent and m ulti m ark e t high - p erf or manc e dr bl ad e 5 mm x 5 mm x 0.6 mm iqfn td a21 310 dat a she et revision 2.1 , 2013 - 09 - 05
edition 2013 - 09 - 05 published by infineon technologies ag 81726 munich, germany ? 2013 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non - infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life - support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life - support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
tda2 1310 data sheet 3 revision 2.1 , 2013 - 09 - 05 revision history page or item su bjects (major changes since previous revision) revision 2.1 2013 - 09 - 05 temperature ri s e diagram added trademarks of infineon technologies ag aurix?, bluemoon?, c166?, canpak?, cipos?, cipurse?, comneon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobridge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my - d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pro - sil?, profet?, rasic?, reversave? , satric?, sieget?, sindrion?, sipmos?, smarti?, smartlewis?, solid flash?, tempfet?, thinq!?, trenchstop?, tricore?, x - gold?, x - pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent technologies, amba?, arm?, multi - ice?, keil?, primecell?, realview?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat - iq? of dect foru m. colossus?, firstgps? of trimble navigation ltd. emv? of emvco, llc (visa holdings inc.). epcos? of epcos ag. flexgo? of microsoft corporation. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission elect rotechnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mif are? of nxp. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red ha t? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius satellite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektronix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex li mited . last trademarks update 2010 - 10 - 26
TDA21310 applications data sheet 4 revision 2.1 , 2013 - 09 - 05 1 applications ? desktop and server buck - converter ? single phase and multiphase pol ? cpu/gpu regulation in desktop graphics cards, ddr memory, graphic memory ? high power density voltage regulator modules (vrm). 2 features ? compatible to intel ? vr1 2 driver and mosfets module (drmos) functionality for desktop/server applications ? for synchronous b uck converter step down voltage applications ? power mosfets rated 25 v for safe operation under all conditions ? f ast switching technology for improve d performance at h igh switching frequencies (> 1 m hz) ? +5 v h igh side and l ow s ide mosfets driving voltage ? compatible to standard +3.3 v pwm controller integrated circuits ? small package: lg - uiqfn - 32 - 2 (5 x 5 x 0.6 mm3) ? optimized footprint for improved cooling by the pcb ? dc output current up to 40 a ? 94% peak efficiency at 1.2v 1 ? dc i nput voltage up to +16 v ? remote driver disable function ? includes bootstrap diode ? undervoltage lockout ? shoot through protection ? tri - state pwm input functionality ? top s ide cooling ? rohs compliant table 1 product identification part number temp range package marking TDA21310 - 25 ? ? figure 1 picture of the product 1 typical p ower stage efficiency, v in =12v, v drv =v cin =5v, f sw =300khz, l=210nh, 0 .2m , no air flow, no heat sink.
TDA21310 description data sheet 5 revision 2.1 , 2013 - 09 - 05 3 description 3.1 pinout figure 2 pinout, n umbering and n ame of p ins (transparent top view) table 2 i/o signals pin no. name pin type buffer type function 4 pwm i +3.3 v logic pwm drive logic input the tri - state pwm input is compatible with 3.3 v. 5 dr_en i +3.3 v logic enable signal (active high ) connect to gnd to disable the ic. 6 boot i analog bootstrap voltage pin connect to boot capacitor 7 phase i analog switch node (reference for boot voltage) internally connected to vswh pin, connect to boot capacitor 12, 25 to 29, vswh pad vswh o analog switch node output high current output switching node v s w h v s w h v s w h v s w h v c i n v s w h n c p w m v i n p h a s e b o o t c g n d v d r v n c d r _ e n v i n v i n v i n v s w h p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d p i n # 1 p i n # 2 p i n # 3 p i n # 4 p i n # 5 p i n # 6 p i n # 7 p i n # 8 p i n # 9 p i n # 1 0 p i n # 1 1 p i n # 1 2 p i n # 1 3 p i n # 1 4 p i n # 1 5 p i n # 1 6 p i n # 1 7 p i n # 1 8 p i n # 1 9 p i n # 2 0 p i n # 2 1 p i n # 2 2 p i n # 2 3 p i n # 2 4 p i n # 2 5 p i n # 2 6 p i n # 2 7 p i n # 2 8 p i n # 2 9 p i n # 3 0 p i n # 3 1 p i n # 3 2 v i n v s w h p g n d
TDA21310 description data sheet 6 revision 2.1 , 2013 - 09 - 05 table 3 power supply pin no. name pin type buffer type function 8 to 11, vin pad vin power C input voltage supply of the drain of the h igh s ide mosfet 31 vdrv power C fet gate supply voltage high and l ow s ide mosfets gate drive supply 32 vcin power C logic supply voltage 5 v bias voltage for the internal logic table 4 ground pins pin no. name pin type buffer type function 1 cgnd gnd C control signal ground should be connected to pgnd externally 13 to 24, 30 pgnd gnd C power ground all these pins must be connected to the power gnd plane through multiple low inductance vias. table 5 not connected pin no. name pin type buffer type function 2, 3 nc C C no internal connection leave pin floating or tie to gnd.
TDA21310 description data sheet 7 revision 2.1 , 2013 - 09 - 05 3.2 general description the infineon TDA21310 is a multichip module that incorporates infineons premier mosfet technology for a single high side and a single low side mosfet coupled with a robust, high performance, high switching freq uency gate driver in a single 32 pin lg - uiqfn - 32 - 2 package. the optimized gate timing allows for significant light load efficiency improvements over discrete solutions. state of the art mosfet technology provides exceptional full load performance. when combined with infineons f amily of d igital m ulti - phas e c ontrollers, the TDA21310 forms a complete core - voltage regulator solution for advanced micro and graphics processors as well as point - of - load applications. the TDA21310 is not pin compatible to the intel 6x6 drmos specification , but compatible by functionality . the d evice package height is only 0.6 mm, and is an excellent choice for applications with critical height limitations. it has reduced thermal impedance from junction to top case compared to drmos, allowing for top side cooling. figure 3 simplified block diagram attention: gh and gl are not accessible . they are mentioned for clarity in this block diagram. d r _ e n p g n d v s w h h s d r i v e r l s d r i v e r u v l o l s l o g i c i n p u t l o g i c t r i - s t a t e p w m v c i n v d r v c g n d g l b o o t v i n d r i v e r i c p h a s e l s m o s f e t v d r v v d r v l e v e l s h i f t e r h s l o g i c 5 0 0 k c g n d 7 k 1 c g n d 1 6 k 5 v c i n 1 0 k 1 0 k + + - - h s m o s f e t s h o o t t h r o u g h p r o t e c t i o n u n i t g h
TDA21310 electrical specification data sheet 8 revision 2.1 , 2013 - 09 - 05 4 electrical s pecification 4.1 absolute maxi mum ratings note: t a = 25c stresses above those listed in table 6 absolute maximum ratings may cause permanent damage to the device. these are absolute stress ratings only and operation of the device is not implied or recommended at these or any other con ditions in excess of those given in the operational sections of this specification. exposure over values of the recommended ratings (table 8) for extended periods may adversely affect the operation and reliability of the device. table 6 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. frequency of the pwm input f sw C C C out C C C in (dc) - 0.30 C cin (dc) - 0.30 C C drv (dc) - 0.30 C C swh (dc) - 1 C C swh (ac) - 10 2 C C phase (dc) - 1 C C phase (ac) - 10 C C boot (dc) - 0.3 C C boot (ac) - 1 2 C C boot - phase (dc) - 1 C C dr_en - 0.3 C C pwm - 0.3 C C jmax - 40 C ? C stg - 5 5 C C note: all rated voltages are relative to voltages on the cgnd and pgnd pins unless otherwise specified. 2 ac is limited to 10 ns
TDA21310 electrical specification data sheet 9 revision 2.1 , 2013 - 09 - 05 4.2 thermal characteristics table 7 thermal characteristics parameter symbol values unit note / test condition min. typ. max. thermal resistance between driver junction and soldering point 3 js - driver C 29 C k/w C thermal resistance between driver junction and top of package jtop - driver C 14 C C thermal resistance between h igh - s ide mosfet junction and soldering point 3 js - hs C 2 C C thermal resistance between h igh - s ide mosfet junction and top of package jtop - hs C 7 C C thermal resistance between l ow - s ide mosfet junction and soldering point 3 js - ls C 1 C C thermal resistance between l ow - s ide mosfet junction and top of package jtop - ls C 2 C C thermal resistance between driver junct ion and high - s ide mosfet junction j j - driver - hs C 40 C thermal resistance between driver junction and l ow - s ide mosfet junction j j - driver - ls C 60 C thermal resistance between l ow - s ide mosfet junction and h igh - s ide mosfet junction j j - ls - hs C 36 C 4.3 recommended operating conditions and electrical characteristics note: v drv = v cin = 5 v, t a = 25c table 8 recommended operating conditions parameter symbol values unit note / test condition min. typ. max. input voltage v in 5 C 16 v C mosfet driver voltage v drv 4.5 5 6 C logic supply voltage v cin 4.5 5 6 v cin rising ,3.3v to 3.9v: dv cin /dt > 3 00 v/s junction temperature t jop - 25 C 125 c C 3 the junction - soldering point is referred to the bottom exposed pad.
TDA21310 electrical specification data sheet 10 revision 2.1 , 2013 - 09 - 05 table 9 voltage supply and biasing current parameter symbol values unit note / test condition min. typ. max. uvlo rising v uvlo_r C C cin rising,3.3v to 3.9v: dv cin /dt > 3 00v/s uvlo falling v uvlo_f C C i vdrv_300khz C C f sw = 300 khz i vdrv_1mhz C C f sw = 1 mhz i vdrv_pwml C C a dr_en = 3.3 v, pwm = 0 v i vdrv_pwmh C C dr_en = 0v, pwm = 3.3v ic current (control) i vcin_pwml C C i vcin_o C C i cin + i drv C C table 10 logic inputs and threshold parameter symbol values unit note / test condition min. typ. max. dr_en input low v dr_en _l 0.7 1.1 1.3 v v dr_en falling input high v dr_en _h 1.9 2.1 2.4 v dr_en rising sink current i dr_en C C a dr_en = 1 v pwm input low v pwm_l C C pwm falling input high v pwm_h 2.4 C C pwm rising input resistance r in - pwm 3 5 7 k ? pwm = 1 v open voltage v pwm_o C C pwm_o tri - state shutdown window 4 v pwm_s 1.2 C C 4 maximum voltage range for tri - state
TDA21310 theory of operation data sheet 11 revision 2.1 , 2013 - 09 - 05 table 11 timing characteristics parameter symbol values unit note / test condition min. typ. max. pwm tri - s tate to vswh rising delay or vswh falling delay t _pts C C C C C C C C C C C C C C C C 5 theory of operation the TDA21310 incorporates a high performance gate driver, one high - side power mosfet and one low - side power mosfet in a single 32 pin lg - uiqfn - 32 - 2 package. the advantages of this arrangement are found in the areas of increased performance, increased efficiency and lower overall package and layout inductance. this module is ideal for use in syn chronous buck regulators . the power mosfets are optimized for 5 v gate drive enabling excellent high load and light load efficiency. the gate driver is a robust high - performance driver rated at the switching node for dc voltages ranging from - 1 v to + 16 v. t he power density for transmitted power in a multiphase regulator of this approach can easily be higher than 4 0 w per phase within a 25 mm 2 area. 5.1 driver characteristics the gate driver of the TDA21310 has two input voltage s , vcin and vdrv. vcin is the 5 v logic supply for the driver. vdrv sets the driving voltage for the high side and low side mosfets. the reference for the gate driver control circuit (vcin) is cgnd. to decouple the sensitive control circuitry (logic supply) from a noisy environment a ceramic capacitor must be placed between vcin and cgnd close to the pins. vdrv needs also to be decoupled using a ceramic capacitor (mlcc) between vdrv and pgnd in close proximity to the pins. pgnd serves as refer ence for the power circuitry including the driver output stage. referring to the block diagram page 7 , vcin is internally connected to the uvlo circuit . it will force shut - down for insufficient vcin voltage. vdrv supplies the floating high - side drive C consisting of an active boot circuit - and the low - side drive circuit. a second uvlo circuitry, sensing the boot voltage level, is implemented to prevent false gh t urn on during insufficient power supply level condition (boot c ap charging/discharging sequence). during undervoltage both gh and gl are driven low actively; further passive pull - down ( 1 0 k ? ) is placed across gate - source of both fets .
TDA21310 theory of operation data sheet 12 revision 2.1 , 2013 - 09 - 05 figure 4 internal output signal from uvlo unit 5.2 inputs to the internal control circuits the pwm is the control input to the ic from an external pwm controller and is compatible with 3.3 v. the pwm input has tri - state functionali ty. when the voltage remains in the specified pwm - shutdown - window for at least the pwm - shutdown - holdoff time t _tsshd , the operation will be suspended by keeping both mosfet gate outputs low. once left open, the pin is held internally at a level of v pwm_o = 1.5 v level . table 12 pwm pin functionality pwm logic level driver output low gl= high, gh = low high gl = low, gh = high open (left floating, or h igh impedance) gl = low, gh = low using a wide range vcin power supply (from 4.5 v to 6 v) causes a shifting in the threshold voltages for the following parameters: v pmw_o , v pwm_h , v pwm_l . the typical behavior of these thresholds over vcin voltage variation is shown in the following graph. v cin h l v uvlo_f v uvlo_r uvlo output logic level shutdown enable
TDA21310 theory of operation data sheet 13 revision 2.1 , 2013 - 09 - 05 figure 5 variation of pwm l evels versus vcin l ogic s upply v oltage attention: the vpwm_s is also temperature dependent. vcin requires a minimum dv/dt of 300v/ s in the vicinity of the uvlo threshold to prevent the driver logic from emitting any gate drive glitches. the dr_en is an active high signal. when dr_en is pul led lo w, the power stage is disabled. table 13 dr_en pin functionality dr_en logic level driver output low shutdown : gl = gh = low high enable : gl = gh = active open (left floating, or h igh impedance) shutdown : gl = gh = low 5.3 shoot through protection the TDA21310 driver includes gate drive functionality to protect against shoot through. in order to protect the p ower stage from overlap, both h igh - s ide and l ow - s ide mosfets being on at the same time, the adaptive c ontrol circuitry monitors specific voltages. when the pwm signal transitions to low, the h igh - s ide mosfet will begin to turn off after the propagation dela y time t_pdlu. when v gs of the h igh - s ide mosfet is discharged below 1 v ( a threshold below which the h igh - s ide mosfet is off) , a secondary delay t _pdhl is initiated . after that delay the l ow - s ide mosfet turns on regardless of the state of the vswh pin. it ensures that the converter can sink current efficiently and the bootstrap capacitor will be refres hed appropriately during each swi tching cycle. see figure 8 for more detail.
TDA21310 application data sheet 14 revision 2.1 , 2013 - 09 - 05 6 application 6.1 implementation figure 6 pin i nterconnection o utline (transparent top view) note: 1. pin phase is internally connected to vswh node 2. it is recommended to place a rc filter between vcin and vdrv as shown. 3. during power - up and down sequences, the pwm signal must be either low or tri - state (open vo ltage), but never high, in order to avoid uncontrolled output voltage. v s w h v i n 1 2 3 4 5 6 7 8 9 1 6 1 7 2 5 v i n v s w h p g n d p w m v s w h 1 0 1 1 1 2 1 3 1 4 1 5 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 2 3 1 3 0 2 9 2 8 2 7 2 6 v i n p h a s e b o o t v d r v v c i n d r _ e n p g n d 4 7 0 n f 4 x 1 0 f c i n v i n c b o o t + 5 v p w m ( 4 . 5 v - 1 6 v ) 1 f 1 f 1 p g n d n c n c c g n d v o u t l c o u t
TDA21310 application data sheet 15 revision 2.1 , 2013 - 09 - 05 6.2 typical application figure 7 four - phase voltage regulator - typical application (simplified schematic)
TDA21310 gate driver timing diagram data sheet 16 revision 2.1 , 2013 - 09 - 05 7 gate driver timing diagram figure 8 adaptive g ate driver t iming d iagram figure 9 dr_en t iming d iagram (pwm is assumed high ) dr_en vswh t_pdl(dr_en ) v dr_en _l t_pdh(dr_en ) v dr_en _h active active deactivated tri - state v pwm_l t_tsshd t_pdll t_pdlu v pwm_h v pwm_l t_tssh d t_pts t_pts v pwm_h note : vswh during entering/exit ing tri - state behaves dependen d on inductor current. vswh pwm v pwm_h
TDA21310 performance curves C typical data data sheet 17 revision 2.1 , 2013 - 09 - 05 8 performance curves C typical data operating conditions (unless otherwise specified): vin = +12 v, vcin = vdrv = +5 v , l out = 150nh (cooper, fpi0906 r 1 - r15 , dcr = 0.29 m ) inductor, t a = 25 c, airflow = 3 00 lfm, no heatsink. efficiency and power loss reported herein include only TDA21310 losses. 8.1 t emperature rise figure 10 tempera ture rise over output current
TDA21310 performance curves C typical data data sheet 18 revision 2.1 , 2013 - 09 - 05 8.2 driver current versus switchi g frequency figure 11 driver current over swi tc hing frequency in ccm operation
TDA21310 performance curves C typical data data sheet 19 revision 2.1 , 2013 - 09 - 05 8.3 efficiency and power loss versus switching frequency figure 12 efficiency at vin = 12 v, vcin = vdrv = 5 v, vout = 1.82 v, parameter: f sw figure 13 power loss at vin = 12 v, vcin = vdrv = 5 v, vout = 1.82 v, parameter: f sw
TDA21310 performance curves C typical data data sheet 20 revision 2.1 , 2013 - 09 - 05 figure 14 efficiency at vin = 12 v, vcin = vdrv = 5 v, vout = 1.218 v, parameter: f sw figure 15 power loss at vin = 12 v, vcin = vdrv = 5 v, vout = 1.218 v, parameter: f sw
TDA21310 mechanical drawing lg - uiqfn - 32 - 2 data sheet 21 revision 2.1 , 2013 - 09 - 05 9 mechanical drawing lg - uiqfn - 32 - 2 figure 16 mechanical d imensions
TDA21310 mech anical drawing lg - uiqfn - 32 - 2 data sheet 22 revision 2.1 , 2013 - 09 - 05 figure 17 stencil d imensions (in mm)
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